Realization of Advanced Encryption Standard for Power and Area optimization

An AES algorithm can be implemented in software or hardware but hardware implementation is more suitable for high speed applications.AES is most secure security algorithm to maintain safety and reliability of date transmission for this key size is important. And here used AES-256 bit.The main goal of paper is AES hardware implementation to achieve less area and low power consumptions also to achieve high speed data processing and reduce time for key generation. This paper presents AES-256 bit algorithm design consist of 128 bit symmetric key. Xilinx ISE.14.7(64-bit) is used for simulation by using VHDL and hardware implementation on FPGA(Xilinx Spartan 6 or Altera Cyclone 2 FPGA device). KeywordsCryptography, Cipher, FPGA, Advanced Encryption Standard(AES),VHDL __________________________________________________*****_________________________________________________